Faculty Profile - VCU Engineering

Dr. Robert H. Klenke

Associate Professor, Department of Electrical and Computer Engineering

E-mail: rhklenke@vcu.edu
Phone: (804) 827-7007
Fax: (804) 827-0006
Website: http://www.people.vcu.edu/~rhklenke/

601 West Main Street, Room 222
P.O. Box 843072
Richmond, Virginia 23284-3072

Secretary: Dorothy Kelley
dckelley@vcu.edu
Phone: (804) 828-0181

The Design of an Intelligent Control System for Appliances - BTR Siebe Control Systems
A Command, Control and Communications (C3) Enhanced Network Technology Simulation (CENTS) - U.S. Air Force Wright Labs SBIR through EDAptive Computing, Inc.
VHDL 200x - U.S. Air Force Wright Labs

B.S.E.E., Virginia Military Institute, Lexington, VA., 1982
M.S.E.E., University of Virginia, Charlottesville, VA., 1989
Ph.D. Electrical Engineering, University of Virginia, Charlottesville, VA., 1993

Meyassed, M., R. H. Klenke, J. H. Aylor, “Resolving Unknown Inputs in Mixed-Level Simulation with Sequential Elements,” IEEE Transactions On Computers, (to appear).
Klenke, R. H., J. H. Aylor, “An Undergraduate Advanced Computer Design Course Using Virtual-Prototyping,” Proceedings of the IEEE Computer Society International Conference on Microelectronic Systems Education, July 1997, pp 62-63.
Klenke, R. H., M. Meyassed, J. H. Aylor, B. W. Johnson, R. Rao, A. Ghosh, “An Integrated Design Environment for Performance and Dependability Analysis,” Proceedings of the ACM Design Automation Conference, June 1997 pp. 184-189.
Klenke, R. H., J. H. Aylor, R. Hillson, D. J. Kaplan, “VHDL-Based Performance Modeling for the Processing Graph Method Tool (PGMT) Environment,” Proceedings of the VHDL International Users Forum, Spring 1996, pp. 69-73.
Klenke, R. H., J. H. Aylor, J. M. Wolf, “An Analysis of Fault Partitioning Algorithms for Fault Partitioned ATPG,” Proceedings of the IEEE VLSI Test Symposium, April 1996, pp. 231-239.
Klenke, R. H., L. M. Kaufman, J. H. Aylor, R. Waxman, P. Narayan, “Workstation-Based Parallel Test Generation,” Proceedings of the IEEE International Test Conference, October 1993, pp. 419-428.
Klenke, R. H., R. D. Williams, J. H. Aylor, “Parallelization Methods for Circuit Partitioning-Based Parallel Automatic Test Pattern Generation,” Proceedings of the IEEE VLSI Test Symposium, April 1993, pp. 71-78.